The present invention relates to a current mode, digital, PWM control circuit of an output stage, the switching frequencies of which may be forecast and/or predetermined in relation to the operating conditions of the circuit. PWM (Pulse Width Modulation) mode controlled output stages are widely used in a large variety of electronic systems, in particular in driving systems for electric motors, displays, actuators of various kinds, DC--DC converters and battery chargers.
The control circuit drives a power switch (high-side driver or low-side driver), that is commonly constituted by a power transistor, often a field effect transistor, for example a MOSFET, suitable to connect to a supply rail a load circuit, external to the integrated circuit. Commonly the output power transistor is driven by a bistable logic circuit (e.g. a flip-flop). In case of MOSFET type transistors, special techniques such as for example the so-called bootstrapping technique, are employed for optimizing the electrical efficiency of the power switch, by driving the gate of the transistor with a "boosted" voltage (higher than the supply voltage, that is higher than the drain voltage).
Normally the PWM control circuit implements a control of the current flowing through the output stage (current mode control). Optionally, the control circuit may also exert a control of the output voltage, for example in order to limit the voltage applied to an external load. The two control signals (voltage mode and current mode) may be combined logically in order to enable or disable the switching of the power transistor.
To a clock input of the bistable circuit that drives the power switch (for example a D-type flip-flop), may be fed a PWM clock signal, having a certain frequency (f.sub.PWM), that may be derived from a general system's clock of a stable frequency (f.sub.o), for example by employing a frequency divider circuit (1/N). Turn-on control (enabling/disabling switching at the f.sub.PWM frequency) of the power switch may practically be implemented by a logic signal fed to a "reset" input of the driving flip-flop. Such a control signal may be produced by a logic circuit having a plurality of inputs driven by an equal number of logic control signals, for example a logic NOR gate.
According to a classical approach, the current mode control is implemented by employing: a) an error amplifier capable of reading the voltage drop across a sensing resistance, b) a comparator capable of producing a logic level signal and c) a compensation network for the feedback loop. Of course the logic signal that is generated by the comparator may be fed to an input of the logic circuit that controls a reset node of the bistable driving circuit.
This classical approach requires a compensation network and control signals having a particular shape (triangular shape) and may be burdensome in terms of circuit complexity.
It is a main object of the present invention to provide a PWM control circuit implementing a current mode control in a fully digital mode and which does not require the use of an error amplifier.
This objective is fully met by the control circuit of the present invention which is characterized by the fact that it employs two distinct comparators essentially having a different threshold, each comparator being connected in a way as to be able to read the voltage on a sensing resistance, representative of the current flowing through the power switch. This inventive control circuit is useful for battery chargers and DC-to-DC converters, especially battery chargers. A noteworthy advantage of the invention in applications such as battery chargers and converters is that complex feedback loops including capacitances are not required.
A first comparator, having a certain threshold in terms of the level of the current flowing in the power switch, has an output directly connected to a first input of a multi-input control logic circuit of the bistable driving circuit of the output transistor, thus implementing a control system that, in a steady state condition, is essentially an open loop system, as will be described further on in this specification.
The second comparator, having a threshold (in terms of the level of the current flowing in the power switch, higher than the threshold of the first comparator, has an output connected to a second input of the control logic circuit of the driving bistable circuit of the output power transistor. The output of the second comparator also drives a logic circuit capable of generating a turn-on disabling logic signal of the output transistor for a preset period of time following an overtaking of said second current threshold. Also this n.sup.th control logic signal is fed to an n.sup.th input of the control logic circuit of the driving bistable circuit of the output transistor. The multi-input control logic circuit may be constituted by a logic NOR gate or by an equivalent logic circuit.
The current mode control circuit of the invention is capable of handling the occurrence of operating conditions such that, in presence of a long lasting relatively low output voltage, too low for allowing a sufficiently fast and essentially complete discharge of reactive energy through a current recirculation (that is an excessively slow discharge process because of the low recirculation voltage) during off-phases of the output power transistor, would cause an uncontrolled gradual rise of the current. Upon the intervention of the second comparator, when a preset second threshold of the current level is reached, the output transistor is forcibly maintained in an off condition for a preset period of time, which may be sufficient to discharge the accumulated energy. After termination of said preset disabling interval, the circuit "re-attempts" switching by turning on again the output power transistor.
Notwithstanding the fact that a functional, fully digital current mode control may be implemented by employing an hysteresis comparator for reading the level of the output current, such a solution does not permit any control of the switching frequency within the time interval when the current remains in the hysteresis range of the comparator. This may cause the circuit to switch at frequencies that may fall within the audio band or in other bands of interest, and which therefore may produce disturbances in audio systems or similar problems in other types of systems due to the indetermination of the switching frequencies within the hysteresis band of the comparator.